For any chip to function optimally, it must be properly supplied with power. A common technique to improve dynamic power characteristics at switching time involves the addition of capacitance to a ground (Vss) net. This is typically accomplished by utilizing the largest wire size available for the net and/or by adding de-coupling capacitors. Another technique involves connecting dummy metal structures to the Vss net.
During the IC chip fabrication process, a chemical mechanical polishing (CMP) step is one of the final steps performed. The CMP step requires a specific distribution of metal over the surface of the chip. Each fabrication process defines a rectangular region and a minimum metal density for that region. For each such rectangular region of the chip (commonly called a “tile”), the sum of all metal area within the tile divided by the area of the tile must be greater than or equal to the prescribed minimum. If one or more tiles lack the requisite amount of metal, additional metal, referred to as “dummy metal,” is deposited into the region to increase the metal distribution. The dummy metal provides no logical function other than to balance the metal to silicon distribution for the CMP process, and therefore, the dummy metal structure can be of arbitrary shape.
As stated above, the dynamic power characteristics at switching time can be improved if the dummy metal structures are connected to the Vss net. Nevertheless, because dummy metal insertion is performed as one of the final steps of the chip design flow, making these connections in a quick and efficient way is rarely possible.
Accordingly, what is needed is a method for improving dynamic power characteristics of an IC chip by optimizing the capacitance of the Vss net. The present invention addresses such a need.